CY7C09269V

The CY7C09269V/79V/89V and CY7C09369V/79V/89V are high-speed 3.3V synchronous CMOS 16K, 32K, and 64K x 16/18 dual-port static RAMs. Two ports of CY7C09269V are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[6] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data of CY7C09269V is registered for decreased cycle time. Clock to data valid t_CD2 = 6.5 ns[1, 2] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data of CY7C09269V will be available t_CD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via he FT/Pipe pin.

Each port of CY7C09269V contains a burst counter on the input address register. The internal write pulse width is independent of the LOW to HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH on CE₀ or LOW on CE₁ for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables CY7C09269V allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE₀ LOW and CE₁ HIGH to reactivate the outputs.

Counter CY7C09269V enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter CY7C09269V will increment on each LOW to HIGH transition of that port's clock signal. This will read/write one word from/into each successive address location until CNTEN is deasserted. The counter CY7C09269V can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter.

All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.