CY7C09179V

• True Dual-Ported memory cells which allow simultaneous access of the same memory location
• 6 Flow-Through/Pipelined devices
    -32K x 8/9 organizations (CY7C09079V/179V)
    -64K x 8/9 organizations (CY7C09089V/189V)
    -128K x 8/9 organizations (CY7C09099V/199V)
• 3 Modes
    -Flow-Through
    -Pipelined
    -Burst
• Pipelined output mode on both ports allows fast 100-MHz operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[^1]/7.5^[1]/9/12 ns (max.)
• 3.3V low operating power
    -Active= 115 mA (typical)
    -Standby= 10 A (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
    -Shorten cycle times
    -Minimize bus noise
    -Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP

Storage Temperature....................................................................... 65°C to +150°C
Ambient Temperature with Power Applied.........................................55°C to +125°C
Supply Voltage to Ground Potential.......................................................0.5V to +4.6V
DC Voltage Applied to Outputs in High Z State...............................0.5V to V_CC+0.5V
DC Input Voltage.............................................................................0.5V to V_CC+0.5V
Output Current into Outputs (LOW)....................................................................20 mA
Static Discharge Voltage...................................................................................>2001V
Latch-Up Current............................................................................................>200 mA

The CY7C09079V/89V/99V and CY7C09179V/89V/99V are high-speed synchronous CMOS 32K, 64K, and 128K x 8/9 dual-port static RAMs. Two ports are provided, permitting independent, simultaneous access for reads and writes to any location in memory.^[4] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data of CY7C09179V is registered for decreased cycle time. Clock to data valid t_CD2 = 6.5 ns^[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flow-through mode data of CY7C09179V will be available tCD1 = 18 ns after the address is clocked into the device. Pipelined output or flow-through mode is selected via the FT/Pipe pin.

Each port of CY7C09179V contains a burst counter on the input address register. The internal write pulse width is independent of the LOW-to-HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.

A HIGH onCE0 or LOW on CE1 for one clock cycle will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.

Counter enable inputs of CY7C09179V are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter of CY7C09179V will increment on each LOW-to-HIGH transition of that port's clock signal. CY7C09179V will read/write one word from/into each successive address location until CNTEN is deasserted. The counter can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter.

All parts of CY7C09179V are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.