Features: • True dual-ported memory cells which allow simultaneous access of the same memory location• Two Flow-Through/Pipelined devices-32K x 8/9 organizations (CY7C09079A/179A)• Three Modes-Flow-Through-Pipelined-Burst• Pipelined output mode on both ports allows fast 100...
CY7C09179A: Features: • True dual-ported memory cells which allow simultaneous access of the same memory location• Two Flow-Through/Pipelined devices-32K x 8/9 organizations (CY7C09079A/179A)•...
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The CY7C09079A and CY7C09179A are high-speed synchronous CMOS 32k x 8/9 dual-port static RAMs. Two ports of CY7C09179A are provided, permitting independent, simultaneous access for reads and writes to any location in memory.[3] Registers on control, address, and data lines allow for minimal set-up and hold times. In pipelined output mode, data is registered for decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipelined). Flow-through mode can also be used to bypass the pipelined output register to eliminate access latency. In flowthrough mode data will be available tCD1 = 15 ns after the address ofCY7C09179A is clocked into the device. Pipelined output or flowthrough mode is selected via the FT/Pipe pin.
Each port of CY7C09179A contains a burst counter on the input address register. The internal write pulse width is independent of the LOWto- HIGH transition of the clock signal. The internal write pulse is self-timed to allow the shortest possible cycle times.A HIGH on CE0 or LOW on CE1 for one clock cycle CY7C09179A will power down the internal circuitry to reduce the static power consumption. The use of multiple Chip Enables allows easier banking of multiple chips for depth expansion configurations. In the pipelined mode, one cycle is required with CE0 LOW and CE1 HIGH to reactivate the outputs.
Counter CY7C09179A enable inputs are provided to stall the operation of the address input and utilize the internal address generated by the internal counter for fast interleaved memory applications. A port's burst counter is loaded with the port's Address Strobe (ADS). When the port's Count Enable (CNTEN) is asserted, the address counter CY7C09179A will increment on each LOW-to-HIGH transition of that port's clock signal. CY7C09179A will read/write one ord from/into each successive address location until CNTEN is deasserted. The counter CY7C09179A can address the entire memory array and will loop back to the start. Counter Reset (CNTRST) is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack (TQFP) packages.