CY7C0251V

The CY7C024V/025V/026V and CY7C0241V/0251V/036V are low-power CMOS 4K, 8K, and 16K x16/18 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. CY7C0251V can be utilized as standalone 16/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32/36-bit or wider master/ slave dual-port static RAM. An M/S pin is provided for implementing 32/36-bit or wider memory applications without the need for separate master of CY7C0251V and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dualport video/graphics memory.

Each port of CY7C0251V has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic of CY7C0251V is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin.

The CY7C024V/025V/026V and CY7C0241V/0251V/036V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP).