CY7C0241

The CY7C024/0241 and CY7C025/0251 are low-power CMOS 4K x 16/18 and 8K x 16/18 dual-port static RAMs. Various arbitration schemes are included on the CY7C024/0241 and CY7C025/0251 to handle situations when multiple processors access the same piece of data. Two ports are provided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C024/0241 and CY7C025/0251 can be utilized as standalone 16-/18-bit dual-port static RAMs or multiple devices can be combined in order to function as a 32-/36-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 32-/36-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas of CY7C024/0241 and CY7C025/0251 include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/ graphics memory.

Each port of CY7C024/0241 and CY7C025/0251 has independent control pins: Chip Enable (CE), Read or Write Enable (R/W), and Output Enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The Interrupt Flag (INT) permits communication between ports or systems by means of a mail box. The semaphores CY7C024/0241 and CY7C025/0251 are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side of CY7C024/0241 and CY7C025/0251 can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin.

The CY7C024/0241 and CY7C025/0251 are available in 84-pin PLCCs (CY7C024 and CY7C025 only) and 100-pin Thin Quad Plastic Flatpack (TQFP).