CY7C006AV

The CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and 32K x8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are pro-vided, permitting independent, asynchronous access for reads and writes to any location in memory. The CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV can be uti- lized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S</a> pin is provid-ed for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas of CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV include interpro-cessor/multiprocessor designs, communications status buffer-ing, and dual-port video/graphics memory.

Each port of CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV has independent control pins: Chip Enable (CE</a>),Read or Write Enable (R/W</a>), and Output Enable (OE</a>). Twoflags are provided on each port (BUSY</a> and INT</a>). BUSY</a> sig-nals that the port is trying to access the same location currently being accessed by the other port. The Interrupt flag (INT</a>) per-mits communication between ports or systems by means of a mail box. The semaphores of CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV are used to pass a flag, or token,from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side of CY7C138AV/144AV/006AV/007AV and CY7C139AV/145AV/ 016AV/017AV can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared re-source is in use. An automatic power-down feature is con-trolled independently on each port by a Chip Select (CE</a>) pin.