CY74FCT2652T

The FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for multiplexed trans-mission of data directly from the input bus or from the internal storage registers. GAB and GBA control pins are provided to control the transceiver functions. SAB and SBA control pins of FCT2652T are provided to select either real-time or stored data transfer.

The circuitry of FCT2652T used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during transition between stored and real-time data. A LOW input level selects real-time data and a HIGH selects stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by LOW-to-HIGH transitions at the appropriate clock pins (CPAB or CPBA), regardless of the select or enable control pins. When SAB and SBA are in the real-time transfer mode, FCT2652T is also possible to store data without using the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high imped-ance, each set of bus lines will remain at its last state.

On-chip termination resistors FCT2652T are added to the outputs to reduce system noise caused by reflections. The FCT2652T can replace the FCT652T to reduce noise in existing designs. The outputs of FCT2652T are designed with a power-off disable feature to allow for live insertion of boards