CY74FCT162543T

Features:

• FCT-E speed at 3.4 ns
• Power-off disable outputs permits live insertion
• Edge-rate control circuitry for significantly improved noise characteristics
• Typical output skew < 250 ps
• ESD > 2000V
• TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages
• Industrial temperature range of -40°C to +85°C
• V_CC = 5V ± 10%
CY74FCT16543T Features:
• 64 mA sink current, 32 mA source current
• Typical VOLP (ground bounce) <1.0V at V_CC = 5V, T_A = 25°C
CY74FCT162543T Features:
• Balanced 24 mA output drivers
• Reduced system switching noise
• Typical VOLP (ground bounce) <0.6V at V_CC = 5V, T_A= 25°C
CY74FCT162H543T Features:
• Bus hold retains last active state
• Eliminates the need for external pull-up or pull-down resistors


Pinout




Specifications

Storage Temperature .........................................................Com'l -55°C to +125°C
Ambient Temperature with Power Applied ..........................Com'l -55°C to +125°C
DC Input Voltage ...................................................................................-0.5V to +7.0V
DC Output Voltage ................................................................................-0.5V to +7.0V
DC Output Current (Maximum Sink Current/Pin) ..................................-60 to +120 mA
Power Dissipation ................................................................................................1.0W
Static Discharge Voltage..................................................................................>2001V


Description

The CY74FCT16543T and CY74FCT162543T are 16-bit, high-speed, lowpower latched transceivers that are organized as two independent 8-bit D-type latched transceivers containing two sets of eight D-type latches with separate Latch Enable (LEAB, LEAB) and Output Enable (OEAB, OEAB ) controls for each set to permit independent control of inputting and outputting in either direction of data flow. For data flow from A to B, for example, the A-to-B input Enable (CEAB )must be LOWin order to enter data from A or to take data from B as indicated in the truth table. With CAEB LOW, a LOW signal on the A-to-B Latch Enable (LEAB makes the A-to-B latches transparent; a subsequent LOW-to-HIGH transition of the LEAB signal puts the A latches in the storage mode and their outputs no longer change with the A inputs. With CEAB and OEAB both LOW, the three-stateBoutput buffers are active and reflect the data present at the output of the A latches. Control of data from B to A is similar, but uses CEAB , LEAB , and OEAB inputs flow-through pinout and small shrink packaging and in simplifying board design. The output buffers of CY74FCT16543T and CY74FCT162543T are designed with a power-off disable feature to allow live insertion of boards.

The CY74FCT16543T is ideally suited for driving high-capacitance loads and low-impedance backplanes.

The CY74FCT162543T has 24-mA balanced output drivers with current limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162543T is ideal for driving transmission lines.

The CY74FCT162H543T is a 24-mA balanced output part that has "bus hold" on the data inputs. The device retains the input's last state whenever the input goes to high impedance.

This eliminates the need for pull-up/down resistors and prevents floating inputs.