CY62512V

The CY62512V is a high-performance CMOS static RAM organized as 65,536 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE₁), an active HIGH chip enable (CE₂), an active LOW output enable (OE), and three-state drivers. CY62512V has an automatic pow than 99% when deselected.

Writing to the CY62512V is accomplished by taking chip enable one (CE₁) and write enable (WE) inputs LOW and chip enable two (CE₂) input HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is then written into the location specified on the address pins (A₀ through A₁₅).

Reading from the CY62512V is accomplished by taking chip enable one (CE₁) and output enable (OE) LOW while forcing write enable (WE) and chip enable two (CE₂) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.

The eight input/output pins of CY62512V(I/O₀ through I/O₇) are placed in a high-impedance state when the device is deselected (CE₁ HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW). The CY62512V is available in standard 32-pin TSOP type I package.