CY62168EV30

The CY62168EV30 is a high performance CMOS static RAM organized as 2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life™ (MoBL^®) in portable applications such as cellular telephones. The CY62168EV30 also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (Chip Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW). The input and output pins of CY62168EV30(IO₀ through IO₇) are placed in a high impedance state when: the device is deselected (Chip Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW), outputs are disabled (OE HIGH), or a write operation is in progress (Chip Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and WE LOW).

Write to the CY62168EV30 by taking Chip Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input LOW. Data on the eight IO pins (IO₀ through IO₇) is then written into the location specified on the address pins (A₀ through A₂₀).

Read from the CY62168EV30 by taking Chip Enable 1 (CE₁) and Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH while forcing Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the IO pins.

The eight input and output pins of CY62168EV30 (IO₀ through IO₇) are placed in a high impedance state when the device is deselected (CE₁ LOW and CE₂ HIGH), the outputs of CY62168EV30 are disabled (OE HIGH), or a write operation is in progress (CE₁ LOW and CE₂ HIGH and WE LOW). See the "Truth Table" on page 8 for a complete description of read and write modes.