Features: Very high speed: 55 ns
Wide voltage range: 1.65V 2.25V
Ultra low standby power
` Typical standby current: 1.5 µA
`Maximum standby current: 12 µA
Ultra low active power
` Typical active current: 2.2 mA @ f = 1 MHz
Easy memory expansion with CE1, CE2, and OE features
Automatic power down when deselected
CMOS for optimum speed and power
Offered in Pb-free 48-ball VFBGA packagesSpecificationsExceeding the maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ............................... 65°C to + 150°C
Ambient Temperature with
Power Applied .......................................... 55°C to + 125°C
Supply Voltage to Ground
Potential ............................ 0.2V to 2.45V (VCC(max) + 0.2V)
DC Voltage Applied to Outputs
in High Z State[5, 6] .......... 0.2V to 2.45V (VCC(max) + 0.2V)
DC Input Voltage[5, 6] ....... 0.2V to 2.45V (VCC(max) + 0.2V)
Output Current into Outputs (LOW) ............................... 20 mA
Static Discharge Voltage............................................... >2001V
(MIL-STD-883, Method 3015)
Latch up Current........................................................ >200 mADescription
The CY62167EV18 is a high performance CMOS static RAM organized as 1M words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The CY62167EV18 also has an automatic power down feature that reduces power consumption by 99% when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins of CY62167EV18 (IO0 through IO15) are placed in a high impedance state when: the CY62167EV18 is deselected (CE1HIGH or CE2 LOW); outputs are disabled (OE HIGH); both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH); and a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW).
To write to the CY62167EV18, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19).
To read from the CY62167EV18, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory appears on IO8 to IO15. See the Truth Table on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
CY62167EV18 Data Sheet
