CY62147DV18

 The CY62147DV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features ad-vanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The CY62147DV18 also has an automatic power-down feature that significantly reduces power consumption. The CY62147DV18 can also be put into standby mode reducing power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input/output pins of CY62147DV18 (I/O0 through I/O15) are placed in a high-im-pedance state when: deselected (CE HIGH), outputs are dis-abled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CELOW and WE LOW).

Writing to the CY62147DV18 is accomplished by asserting Chip En-able (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins of CY62147DV18(A0 through A17). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A17).
Reading from the CY62147DV18 is accomplished by asserting Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins of CY62147DV18 will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table for a complete description of read and write modes.

The CY62147DV18 is available in a 48-ball FBGA package.