CY62137V18 MoBL2

The CY62137V and CY62137V18 are high-performance CMOS static RAMs organized as 131,072 words by 16 bits.

CY62137V and CY62137V18 features advanced circuit design to provide ultra- low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones.

The CY62137V and CY62137V18 also has an automatic power-down feature that reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH) or when CE is LOW and both BLEand BHE are HIGH. The input/output pins of CY62137V and CY62137V18 (I/O₀ through I/O₁₅) are placed in a high-impedance state when: deselected (CEHIGH), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CELOW, and WE LOW).

Writing to the CY62137V and CY62137V18 is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins of CY62137V and CY62137V18 (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Reading from the CY62137V and CY62137V18 is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the truth table at the back of this data CY62137V and CY62137V18 sheet for a complete description of read and write modes.

The CY62137V and CY62137V18 are available in 48-ball FBGA and standard 44-pin TSOP Type II (forward pinout) packaging.