CY62137FV30

Exceeding the maximum ratings may impair the useful life of thedevice. These user guidelines are not tested.
Storage Temperature ................................ 65 to + 150
Ambient Temperature with
Power Applied ........................................... 55 to + 125
Supply Voltage to Ground
Potential ...........................................................-0.3V to 3.9V
DC Voltage Applied to Outputs
in High Z state ^{[4, 5]} .........................................-0.3V to 3.9V
DC Input Voltage ^{[4, 5]} ...................................0.3V to 3.9V
Output Current into Outputs (LOW) ........................... 20 mA
Static Discharge Voltage ......................................... > 2001V
(MILSTD883, Method 3015)
Latch up Current ................................................... > 200 mA

The CY62137FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The CY62137FV30 also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins of CY62137FV30 (IO₀ through IO₁₅) are placed in a high impedance state in the following conditions:
 ` Deselected (CE HIGH)
 ` Outputs are disabled (OE HIGH
 ` Both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH)
 ` Write operation is active (CE LOW and WE LOW)

Write to the CY62137FV30 by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO₀ through IO₇) is written into the location specified on the address pins (A₀ through A₁₆). If Byte High Enable (BHE) is LOW, then data of CY62137FV30 from IO pins (IO₈ through IO₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Read from the CY62137FV30 by taking Chip Enable (CE) and Output Enable (OE) LOW, while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO₀ to IO₇. If Byte High Enable (BHE) is LOW, then data of CY62137FV30 from memory appears on IO₈ to IO₁₅. See the "Truth Table" on page 9 for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.