CY62137FV18

The CY62137FV18 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The CY62137FV18 also has an automatic power down feature that significantly reduces power consumption when addresses are not toggling. Placing the CY62137FV18 into standby mode reduces power consumption by more than 99% when deselected (CE HIGH or both BLE and BHE are HIGH). The input and output pins (IO0 through IO15) are placed in a high impedance state when:

Deselected (CE HIGH)
Outputs are disabled (OE HIGH)
Both the Byte High Enable and the Byte Low Enable are disabled (BHE, BLE HIGH)
Write operation is active (CE LOW and WE LOW)

To write to the CY62137FV18, take Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins of CY62137FV18 (A0 through A16). If Byte High Enable (BHE) is LOW, then data from IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A16).

To read from the CY62137FV18, take Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from the memory of CY62137FV18 appears on IO8 to IO15. See the "Truth Table" on page 9 for a complete description of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.