CY62136FV30

The CY62136FV30 is a high performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL^®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 90% when addresses are not toggling. Placing the device into standby mode reduces power consumption by  more than 99% when deselected (CE HIGH). The input and output pins (IO₀ through IO₁₅) are placed in a high impedance state when:
` Deselected (CE HIGH)
` Outputs are disabled (OE HIGH)
` Both Byte High Enable and Byte Low Enable are disabled (BHE,BLE HIGH)
` Write operation is active (CE  LOW and WE LOW)

Write to the CY62136FV30 by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO₀ through IO₇) is written into the location specified on the address pins (A₀ through A₁₆). If Byte High Enable (BHE) is LOW, then data from IO pins (IO₈ through IO₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Read from the CY62136FV30 by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins appears on IO₀ to _IO7. If Byte High Enable (BHE) is LOW, then data from memory  appears on IO₈ to IO₁₅. See the "Truth Table" on page 9 for a complete description of read and write modes.

For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.