CY62136CV18

• High Speed
    -55 ns and 70 ns availability
• Low voltage range:
    -1.65V−1.95V
• Pin Compatible with CY62136BV18
• Ultra-low active power
    -Typical Active Current: 0.5 mA @ f = 1 MHz
    -Typical Active Current: 1.5 mA @ f = f_max (70 ns speed)
• Low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• CMOS for optimum speed/power

Storage Temperature ........................................................................... −65°C to +150°C
Ambient Temperature with Power Applied............................................. −55°C to +125°C
Supply Voltage to Ground Potential ...........................................................−0.2V to +2.4V
DC Voltage Applied to Outputs in High Z State^{[3]_{..............................−}}0.2V to V_CC + 0.2V
DC Input Voltage^[3]........................................................................... −0.2V to V_CC + 0.2V
Output Current into Outputs (LOW)......................................................................... 20 mA
Static Discharge Voltage........................................................................................ >2001V
(per MIL-STD-883, Method 3015) Latch-Up Current............................................. >200 mA

The CY62136CV18 is a high-performance CMOS static RAM organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life^® (MoBL^™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling.

The CY62136CV18 can also be put into standby mode when deselected (CE HIGH). The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when: deselected (CE HIGH), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or during a write operation (CE LOW and WE LOW).

Writing to the CY62136CV18 is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A₀ through A₁₆). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Reading from the CY62136CV18 is accomplished by taking Chip Enabl (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/_^O0 to I/O₇. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

The CY62136CV18 is available in 48-ball FBGA packaging.