CY62135V18 MoBL2

The CY62135V18 MoBL2 are high-performance CMOS static RAMs organized as 128K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones.

The CY62135V18 MoBL2 also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when deselected (CE HIGH or CE2 LOW) or when CE is LOW and when CE2 is HIGH and both BLE and BHE are HIGH^[1]. The input/output pins (I/O₀ through I/O₁₅) are placed in a high-impedance state when: deselected (CE HIGH or CE2 LOW), outputs are disabled (OE HIGH), BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, CE2 HIGH and WE LOW).

Writing to the CY62135V18 MoBL2 is accomplished by taking chip enable (CE) LOW, CE2 HIGH, and write enable (WE) inputs LOW. If byte low enable (BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is written into the location specified on the address pins (A0 through A₁₆). If byte high enable (BHE) is LOW, then data from I/O pins (I/O₈ through I/O₁₅) is written into the location specified on the address pins (A₀ through A₁₆).

Reading from the CY62135V18 MoBL2 is accomplished by taking chip enable (CE) LOW, CE2 HIGH, and output enable (OE) LOW while forcing the write enable (WE) HIGH. If byte low enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O₀ to I/O₇. If byte high enable (BHE) is LOW, then data from memory will appear on I/O₈ to I/O₁₅. See the Truth Table at the back of this data sheet for a complete description of read and write modes.

The CY62135V18 MoBL2 are shipped in a wafer form.