CY62128VLL-70SC

DescriptionThe CY62128VLL-70SC belons to CY62128V family which is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIG...

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SeekIC No. : 004319392 Detail

CY62128VLL-70SC: DescriptionThe CY62128VLL-70SC belons to CY62128V family which is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Writing to the device is accomplished by t...

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Part Number:
CY62128VLL-70SC
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/23

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Product Details

Description



Description

The CY62128VLL-70SC belons to CY62128V family which is composed of three high-performance CMOS static RAMs organized as 131,072 words by 8 bits. Writing to the device is accomplished by taking Chip Enable one (CE1) and Write Enable (WE) inputs LOW and the Chip Enable two (CE2) input HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A16). The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs CY62128VLL-70SC are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH, and WE LOW). Easy memory expansion is provided by an active LOW Chip Enable (CE1), an active HIGH Chip Enable (CE2), an active LOW Output Enable (OE) and three-state drivers. These de- vices have an automatic power-down feature, reducing the power consumption by over 99% when deselected. Reading from the device is accomplished by taking Chip En- able one (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable two (CE2) HIGH. Under these conditions, the contents of the memory location speci- fied by the address pins will appear on the I/O pins. The CY62128V family is available in the standard 450-mil-wide SOIC, 32-lead TSOP-I, and STSOP packages.

The features of CY62128VLL-70SC can be summarized as (1)low voltage range: - 2.7V3.6V (CY62128V) - 2.3V2.7V (CY62128V25) - 1.6V2.0V (CY62128V18); (2)low active power and standby power; (3)easy memory expansion with CE and OE features; (4)TTL-compatible inputs and outputs; (5)automatic power-down when deselected; (6)CMOS for optimum speed/power.

The absolute maximum ratings of CY62128VLL-70SC are (1)storage temperature: 65°C to +150°C; (2)ambient temperature with power applied.: 55°C to +125°C; (3)supply voltage to ground potential (Pin 28 to Pin 14): 0.5V to +4.6V; (4)DC voltage applied to outputs in high Z state: 0.5V to VCC + 0.5V; (5)DC input voltage : 0.5V to VCC + 0.5V; (6)output current into outputs (LOW): 20 mA; (7)static discharge voltage (per MIL-STD-883, Method 3015): >2001V; (8)latch-up current: >200 mA.




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