CY62128DV30

Features:

• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
-Typical active current: 0.85 mA @ f = 1 MHz
-Typical active current: 5 mA @ f = f_MAX
• Ultra-low standby power
• Easy memory expansion with CE ₁, CE ₂, and OE features
• Automatic power-down when deselected
• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a 32-lead Short TSOP, and a 32-lead Reverse TSOP


Pinout




Specifications

Storage Temperature ...........................................................................65°C to +150°C
Ambient Temperature with Power Applied.............................................55°C to +125°C
Supply Voltage to Ground Potential ............................................................... −0.3V to 3.9V
DC Voltage Applied to Outputs in High-Z State^[3] ................................−0.3V to VCC + 0.3V
DC Input Voltage^[3] ............................................................................. −0.3V to VCC + 0.3V
Output Current into Outputs (LOW)............................................................................ 20 mA
Static Discharge Voltage.......................................................................................... > 2001V
(per MIL-STD-883, Method 3015) Latch-up Current ............................................... > 200 mA


Description

The CY62128DV30 is a high-performance CMOS static RAM organized as 128K words by 8 bits. This device features advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling.
The device can be put into standby mode reducing power consumption by more than 99% when deselected Chip Enable 1 (CE1 ) HIGH or Chip Enable 2 (CE2 ) LOW. The input/output pins (I/O0 through I/O7) CY62128DV30 are placed in a high-impedance state when: deselected Chip Enable 1 (CE1 ) HIGH or Chip Enable 2 (CE2 ) LOW, outputs are disabled (OE HIGH), or during a write operation (Chip Enable 1 (CE1 ) LOW and Chip Enable 2 (CE2 ) HIGH and Write Enable (WE ) LOW).
Writing to the device is accomplished by taking Chip Enable 1 (CE1 ) LOW with Chip Enable 2 (CE2) HIGH and Write Enable(WE) LOW. Data on the eight I/O pins is then written into the location specified on the Address pin (A0 thro. A16).
Reading from the device is accomplished by taking Chip Enable 1 (CE1 ) LOW with Chip Enable 2 (CE2) HIGH and Output Enable (OE) LOW CY62128DV30 while forcing the Write Enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/Oo through I/O7) CY62128DV30 are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or during a write operation (CE1 LOW, CE2 HIGH), and WE LOW).