CY2SSTV858-32

Features: • Operating frequency: 60 MHz to 230 MHz• Supports 400 MHz DDR SDRAM• 10 differential outputs from one differential input• Spread-Spectrum-compatible• Low jitter (cycle-to-cycle): < 75• Very low skew: < 100 ps• Power management control inpu...

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CY2SSTV858-32 Picture
SeekIC No. : 004319311 Detail

CY2SSTV858-32: Features: • Operating frequency: 60 MHz to 230 MHz• Supports 400 MHz DDR SDRAM• 10 differential outputs from one differential input• Spread-Spectrum-compatible• Low jit...

floor Price/Ceiling Price

Part Number:
CY2SSTV858-32
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Operating frequency: 60 MHz to 230 MHz
• Supports 400 MHz DDR SDRAM
• 10 differential outputs from one differential input
• Spread-Spectrum-compatible
• Low jitter (cycle-to-cycle): < 75
• Very low skew: < 100 ps
• Power management control input
• High-impedance outputs when input clock < 20 MHz
• 2.6V operation
• Pin-compatible with CDC857-2 and -3
• 48-pin TSSOP and 40 QFN package
• Industrial temperature of 40°C to 85°C
• Conforms to JEDEC DDR specification



Pinout

  Connection Diagram


Specifications

Input Voltage Relative to VSS:...............................VSS 0.3V
Input Voltage Relative to VDDQ or AVDD: .......... VDDQ + 0.3V
Storage Temperature: .............................. 65°C to + 150°C
Operating Temperature:.............................. 40°C to +85°C
Maximum Power Supply: ...............................................3.5V



Description

The CY2SSTV858-32 is a high-performance, low-skew, low-jitter zero-delay buffer designed to distribute differential clocks in high-speed applications. The CY2SSTV858-32 generates ten differential pair clock outputs from one differential pair clock input. In addition, the CY2SSTV857-32 features differential feedback clock outpts and inputs. This allows the CY2SSTV858-32 to be used as a zero delay buffer. When used as a zero delay buffer in nested clock trees, the CY2SSTV857-32 locks onto the input reference and translates with near-zero delay to low-skew outputs.




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