Features: • Six ECL/PECL differential outputs• Two ECL/PECL differential inputs• Hot-swappable/-insertable• 50 ps output-to-output skew• 250 ps device-to-device skew• 950 ps propagation delay (typical)• 1.2 GHz Operation• 2.8 ps RMS period jitter (ma...
CY2PP326: Features: • Six ECL/PECL differential outputs• Two ECL/PECL differential inputs• Hot-swappable/-insertable• 50 ps output-to-output skew• 250 ps device-to-device skew...
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Parameter |
Description | Condition |
Min. |
Max. |
Unit |
VCC |
Positive Supply Voltage | Non-Functional |
0.3 |
4.6 |
V |
VEE |
Negative Supply Voltage | Non-Functional |
-4.6 |
0.3 |
V |
TS |
Temperature, Storage | Non-Functional |
65 |
+150 |
°C |
TJ |
Temperature, Junction | Non-Functional |
150 |
°C | |
ESDh |
ESD Protection | Human Body Model |
2000 |
V | |
MSL |
Moisture Sensitivity Level |
3 |
N.A. | ||
Gate Count |
Total Number of Used Gates | Assembled Die |
50 |
gates |
The CY2PP326 is a low-skew, low propagation delay 2 x 2 differential clock, data switch, and fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low-signal skews at operating frequencies of up to 1.5 GHz.
The device features two differential input paths which are multiplexed internally to six outputs grouped in two banks. The muxes are controlled by SEL(0:1) control inputs. The CY2PP326 may function as 1:6 or 2x 1:3 clock/data buffer and as a clock/data repeater or multiplexer.
Since the CY2PP326 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems and for switching data signals between different channels. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2PP326 delivers consistent, guaranteed performance over differing platforms.