Features: • Ten ECL/PECL differential outputs• One ECL/PECL differential or single-ended inputs (CLKA)• One HSTL differential or single-ended inputs (CLKB)• Hot-swappable/-insertable• 29 ps typical output-to-output skew• 95 ps typical part-to-part skew• 40...
CY2DP3110: Features: • Ten ECL/PECL differential outputs• One ECL/PECL differential or single-ended inputs (CLKA)• One HSTL differential or single-ended inputs (CLKB)• Hot-swappable/-in...
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DescriptionThe CY2DP3110A1 is one member of the CY2 series of network circuits that produced using...
DescriptionThe CY2DP3110AI is one member of the CY2 series of network circuits that produced using...
Parameter |
Description | Condition |
Min. |
Max. |
Unit |
VCC |
Positive Supply Voltage | Non-Functional |
0.3 |
4.6 |
V |
VEE |
Negative Supply Voltage | Non-Functional |
-4.6 |
0.3 |
V |
TS |
Temperature, Storage | Non-Functional |
65 |
+150 |
°C |
TJ |
Temperature, Junction | Non-Functional |
150 |
°C | |
ESDh |
ESD Protection | Human Body Model |
2000 |
V | |
MSL |
Moisture Sensitivity Level |
3 |
N.A. | ||
Gate Count |
Total Number of Used Gates | Assembled Die |
50 |
gates |
The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz. The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin.
The CY2DP3110 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL single-ended signal to 10 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01- F capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point.
Since the CY2DP3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3110 delivers consistent performance over various platforms