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CY2DL818

Features: • Low voltage operation• VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pair of LVDS Outputs• Drives either a 50-ohm or 100-ohm load (selectable)• Low input capacitance• Low output skew• Low propagatio...

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SeekIC No. : 004319285 Detail

CY2DL818: Features: • Low voltage operation• VDD = 3.3V• 1:8 fanout• Single-input-configurable for LVDS, LVPECL, or LVTTL• 8 pair of LVDS Outputs• Drives either a 50-ohm or...

CY2DL818 Data Sheet

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Part Number:
CY2DL818
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Low voltage operation
• VDD = 3.3V
• 1:8 fanout
• Single-input-configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVDS Outputs
• Drives either a 50-ohm or 100-ohm load (selectable)
• Low input capacitance
• Low output skew
• Low propagation delay
• Typical (tpd < 4 ns)
• Packages available include: TSSOP
• Does not exceed Bellcore 802.3 standards
• Operation at => 350 MHz 700 Mbps


Pinout

Connection Diagram


Specifications

Storage Temperature: ................................65°C to + 150°C
Ambient Temperature:...................................40°C to +85°C
Supply Voltage to Ground Potential
(Inputs and VCC only)....................................... 0.3V to 4.6V
Supply Voltage to Ground Potential
(Outputs only) ........................................ 0.3V to VDD + 0.3V
DC Input Voltage ................................... 0.3V to VDD + 0.3V
DC Output Voltage................................. 0.3V to VDD + 0.9V
Power Dissipation........................................................ 0.75W


Description

This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry's fastest logic.

The Cypress CY2DL818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVDS output pairs.

Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals.

The Cypress CY2DL818 has configurable input and output functions. The input can be selectable for LVCMOS/LVTTL, LVPECL, or LVDS signals, while the output drivers support standard and high-drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.




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