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CY29943

Features: • 200-MHz clock support• 2.5V or 3.3V operation• LVPECL clock input• LVCMOS-/LVTTL-compatible inputs• 18 clock outputs: drive up to 36 clock lines• 200 ps max. output-to-output skew• Output Enable control• Pin compatible with MPC942P•...

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SeekIC No. : 004319271 Detail

CY29943: Features: • 200-MHz clock support• 2.5V or 3.3V operation• LVPECL clock input• LVCMOS-/LVTTL-compatible inputs• 18 clock outputs: drive up to 36 clock lines• 200 ...

CY29943 Data Sheet

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Part Number:
CY29943
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Features:

• 200-MHz clock support
• 2.5V or 3.3V operation
• LVPECL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942P
• Available in Industrial and Commercial
• 32-pin LQFP package


Pinout

Connection Diagram


Specifications

Maximum Input Voltage Relative to VSS: ............. VSS 0.3V
Maximum Input Voltage Relative to VDD:.............VDD + 0.3V
Storage Temperature: ................................65°C to + 150°C
Operating Temperature: ................................40°C to +85°C
Maximum ESD protection ............................................... 2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).


Description

The CY29943 is a low-voltage 200-MHz clock distribution buffer with an LVPECL-compatible input clock. All other control inputs are LVCMOS-/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS- or LVTTL-compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission line, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29943 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.




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