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CY29940-1

Features: • 200-MHz clock support• LVPECL or LVCMOS/LVTTL clock input• LVCMOS/LVTTL-compatible inputs• 18 clock outputs: drive up to 36 clock lines• 150 ps max. output-to-output skew• 23 output impedance• Dual or single supply operation:-3.3V core and 3.3V...

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SeekIC No. : 004319269 Detail

CY29940-1: Features: • 200-MHz clock support• LVPECL or LVCMOS/LVTTL clock input• LVCMOS/LVTTL-compatible inputs• 18 clock outputs: drive up to 36 clock lines• 150 ps max. output-...

CY29940-1 Data Sheet

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Part Number:
CY29940-1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• 200-MHz clock support
• LVPECL or LVCMOS/LVTTL clock input
• LVCMOS/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 150 ps max. output-to-output skew
• 23 output impedance
• Dual or single supply operation:
-3.3V core and 3.3V outputs
-3.3V core and 2.5V outputs
-2.5V core and 2.5V outputs
• Pin-compatible with MPC940L, MPC9109
• Available in commercial and industrial temperature ranges
• 32-pin TQFP package


Pinout

Connection Diagram


Specifications

Maximum Input Voltage Relative to VSS: ............ VSS 0.3V
Maximum Input Voltage Relative to VDD: .............VDD + 0.3V
Storage Temperature: ................................65°C to + 150°C
Operating Temperature: ................................40°C to +85°C
Maximum ESD Protection...............................................2 kV
Maximum Power Supply: ................................................5.5V
Maximum Input Current: ............................................±20 mA
This device contains circuitry to protect the inputs against
damage due to high static voltages or electric field; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, Vin and Vout should be constrained to the
range:
VSS < (Vin or Vout) < VDD
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).


Description

The CY29940-1 is a low-voltage 200-MHz clock distribution buffer with the capability to select either a differential LVPECLor a LVCMOS/LVTTL-compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V or 3.3V LVCMOS/LVTTL-compatible and can drive 50 series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:36. Low output-to-output skews make the CY29940-1 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems.




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