CY27H010

Features:

• CMOS for optimum speed/power
• High speed
   -t_AA = 25 ns max. (commercial)
   -t_AA = 35 ns max. (military)
• Low power
   -275 mW max.
   -Less than 85 mW when deselected
• Byte-wide memory organization
• 100% reprogrammable in thewindowed package
• EPROM technology
• Capable of withstanding >2001V static discharge
• Available in
   -32-pin PLCC
   -32-pin TSOP-I
   -32-pin, 600-mil plastic or hermetic DIP
   -32-pin hermetic LCC


Pinout




Specifications

Storage Temperature ................................. 65°C to +150°C
Ambient Temperature with
Power Applied............................................. 55°C to +125°C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +5.5V
DC Input Voltage............................................ 3.0V to +7.0V
Transient Input Voltage ................................3.0V for <20 ns
DC Program Voltage.......................................................13.0V
UV Erasure................................................... 7258 Wsec/cm2
Static Discharge Voltage ........................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA

Description

The CY27H010 is a high-performance, 1-megabit CMOS EPROM organized in 128 Kbytes. It is available in industryindustry- standard 32-pin, 600-mil DIP, LCC, PLCC, and TSOP-I packages. These devices offer high-density storage combined with 40-MHz performance. The CY27H010 is available in windowed and opaque packages. Windowed packages allow the device to be erased with UV light for 100% reprogrammability.

The CY27H010 is equipped with a power-down chip enable (CE) input and output enable (OE). When CE is deasserted, the device powers down to a low-power stand-by mode. The OE pin three-states the outputs without putting the device into stand-by mode. While CE offers lower power, OE provides a more rapid transition to and from three-stated outputs.

The memory cells utilize proven EPROM floating-gate technology and byte-wide intelligent programming algorithms. The EPROM cell requires only 12.75 V for the supervoltage and low programming current allows for gang programming. The device allows for each memory location to be tested 100%, because each location is written to, erased, and repeatedly exercised prior to encapsulation. Each device is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming.

The CY27H010 is read by asserting both the CE and the OE inputs. The contents of the memory location selected by the address on inputs A₁₆A₀ will appear at the outputs O₇O₀.