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CY23020-1

Features: • 335 ps max Total Timing Budget™ (TTB)™ window• 2.5V or 3.3V outputs• 20 LVCMOS outputs• 50 MHz to 200 MHz output frequency• 50 MHz to 200 MHz input frequency• Integrated phase-locked loop (PLL) with lock indicator• Spread Aware͐...

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SeekIC No. : 004319143 Detail

CY23020-1: Features: • 335 ps max Total Timing Budget™ (TTB)™ window• 2.5V or 3.3V outputs• 20 LVCMOS outputs• 50 MHz to 200 MHz output frequency• 50 MHz to 200 MHz in...

CY23020-1 Data Sheet

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Part Number:
CY23020-1
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/30

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Product Details

Description



Features:

• 335 ps max Total Timing Budget™ (TTB)™ window
• 2.5V or 3.3V outputs
• 20 LVCMOS outputs
• 50 MHz to 200 MHz output frequency
• 50 MHz to 200 MHz input frequency
• Integrated phase-locked loop (PLL) with lock indicator
• Spread Aware™-designed to work with SSFTG
   reference signals
• 3.3V core power supply
• Available in 48-pin TSSOP and QFN packages


Pinout

Connection Diagram


Specifications

Parameter Description Test Conditions Unit
VDD Voltage on any VDD pin with respect to GND 0.5 to +5 V
VIN Voltage on any input pin with respect to GND 0.5 to VDD + 0.5 V
TSTG Storage Temperature 65 to +150 °C
TA Operation Temperature (TSSOP) 0 to +70 °C
Operation Temperature (QFN) 40 to +85 °C
TJ Junction Temperature +150 max °C
PD Package Power Dissipation (TSSOP) 1 W



Description

The CY23020-1-1 is a high-performance 200-MHz PLL-based zero delay buffer designed for high-speed clock distribution applications. The device features a guaranteed TTB window specifying all occurrences of output clocks with respect to the input reference clock across variations in output frequency, supply voltage, operating temperature, input edge rate, and process.

The CY23020-1 outputs are three-state when S1 = S2 = 0 for reduced power. When S1 = 1 and S2 = 0 the PLL is bypassed and the CY23020-1 functions as a fan-out buffer.




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