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CY22150

Features: • Integrated phase-locked loop (PLL)• Commercial and industrial operation• Flash-programmable• Field-programmable• 2-wire serial programming interface• Low-skew, low-jitter, high-accuracy outputs• 3.3V operation with 2.5V output option• 16-...

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SeekIC No. : 004319112 Detail

CY22150: Features: • Integrated phase-locked loop (PLL)• Commercial and industrial operation• Flash-programmable• Field-programmable• 2-wire serial programming interface• ...

CY22150 Data Sheet

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Part Number:
CY22150
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Integrated phase-locked loop (PLL)
• Commercial and industrial operation
• Flash-programmable
• Field-programmable
• 2-wire serial programming interface
• Low-skew, low-jitter, high-accuracy outputs
• 3.3V operation with 2.5V output option
• 16-lead TSSOP


Application

Jitter is defined in many ways including: phase noise,long-term jitter, cycle to cycle jitter, period jitter, absolute jitter,and deterministic. These jitter terms are usually given in terms of rms, peak to peak, or in the case of phase noise dBC/Hz with respect to the fundamental frequency. Power Supply Noise and clock output loading are two major system sources of clock jitter. Power Supply noise can be mitigated by proper power supply decoupling (0.1 µF ceramic cap 0.25") of the clock and ensuring a low impedance ground to the chip. Reducing capacitive clock output loading to a minimum lowers current spikes on the clock edges and thus reduces jitter.
Reducing the total number of active outputs will also reduce jitter in a linear fashion. However, it is better to use two outputs to drive two loads than one output to drive two loads.


Pinout

Connection Diagram


Specifications

Parameter Description Min. Max. Unit
VDD Supply Voltage 0.5 7.0 V
VVDDL I/O Supply Voltage 0.5 7.0 V
TS Storage Temperature[3] 65 125 °C
TJ Junction Temperature   125 °C
  Package Power Dissipation-Commercial Temp   450 mW
  Package Power Dissipation-Industrial Temp   380 mW
  Digital Inputs AVSS 0.3 AVDD + 0.3 V
  Digital Outputs referred to VDD AVSS 0.3 AVDD + 0.3 V
  Digital Outputs referred to VDDL AVSS 0.3 VDDL +0.3 V
ESD Static Discharge Voltage per MIL-STD-833, Method 3015   2000 V



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