CY101E383

The CY101E383 is a new-generation TTL-to-ECL and ECL-to-TTL logic level translator designed for high-performance systems. The device contains ten independent TTL-to-ECL and ten independent ECL-to-TTL translators for high-speed full-duplex data transmission, mixed logic, and bus applications. The CY101E383 is especially suited to drive ECL backplanes between TTL boards. The CY101E383 is implemented with differential ECL I/O to provide balanced low noise operation over controlled impedance buses between TTL and/or ECL subsystems. In addition, the device has internal output 2 kW pull-down resistors tied to VEE to decrease the number of external components. For system testing purposes or for driving light loads, the 2 kW is used as the only termination thereby eliminating up to 20 external resistors.

The part meets standard 100K logic levels with the internal pull-down while driving 50W to -2V.

The device is designed with ample ground pins to reduce bounce, and has separate ECL and TTL power/ground pins toreduce noise coupling between logic families. The parts can operate in single- or dual-supply configurations while maintaining absolute and 100K level swings. The translators are offered in a standard 100K ECL-compatible version with -5.2V or -4.5V power supply. The TTL I/O is fully TTL compatible.

The CY101E383 is packaged in 84-pin surface-mountable PLCCs and CLCCs. To save board space, an 80-pin PQFP package with 25-mil-lead pitch is available.