CSPT857D

Features: SpecificationsDescriptionThe CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT,FBOUT). External feed...

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SeekIC No. : 004317055 Detail

CSPT857D: Features: SpecificationsDescriptionThe CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pair...

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Part Number:
CSPT857D
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:






Specifications






Description

The CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT,FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the input frequency falls below approximately 20MHz, the device will enter power down mode. In this mode,the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption of less than 200A.

The CSPT857D requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPT857D,designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source.

The CSPT857D is available in Commercial Temperature Range (0°C to+70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details.

The CSPT857D has 12 features.The first one is 1 to 10 differential clock distribution.The second one is Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage.The third one is Operating frequency: 60MHz to 220MHz.The fourth one is Very low skew: <100ps for PC1600 - PC2700, <75ps for PC3200.The fifth one is Very low jitter: <75ps for PC1600 - PC2700, <50ps for PC3200.The sixth one is 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700.The seventh one is 2.6V AVDD and 2.6V VDDQ for PC3200.The eighth one is CMOS control signal input.The ninth one is Test mode enables buffers while disabling PLL.The tenth one is Low current power-down mode.The eleventh one is Tolerant of Spread Spectrum input clock.The twelfth one is Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56-pin VFBGA packages.






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