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CS86

Features: • Technology : 0.18 mm silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahighspeed or low-leakage process cell together. • Supply voltage : +1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V• Junction tempe...

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SeekIC No. : 004316791 Detail

CS86: Features: • Technology : 0.18 mm silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahighspeed or low-leakage process cell...

CS86 Data Sheet

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Part Number:
CS86
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/12/21

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Product Details

Description



Features:

• Technology : 0.18 mm silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahighspeed or low-leakage process cell together.
• Supply voltage : +1.8 V ± 0.15 V (normal) to +1.1 V ± 0.1 V
• Junction temperature range : -40 °C to +125 °C
• Cell set
-CS86MN : Offers standard transistor characteristics. Designed as a library for products requiring higher throughputs.
-CS86MZ : Offers transistor characteristics suited for ultra high-speed operation, although the current leakage is larger than that of the CS86MN. Designed as a library for products requiring ultra high-speed processing.
-CS86ML : Offers transistor charactersistics with decreased leak currents. Designed as a library for mobile devices and other products requiring lower power consumption.
• Output buffer cells with noise reduction circuits
• Input buffer cells and bidirectional buffer cells with on-chip input pull-up/pull-down resistors
• Buffer cells for crystal oscillation circuits
• Special interfaces : SSTL2, PCI, P-CML, T-LVTTL, USB 2.0, IEEE1394, and others.
• IP macros : CPU (ARM9, FR-V, and others) , DSP, PCI, IEEE1394, USB 2.0, IrDA, PLL, DAC, ADC, and others.
• Capable of incorporating compiled cells (RAM/ROM/Register file/Delay line)
• Configurable internal bus circuits
• Advanced hardware/software co-design environment
• Short-term development using Physical Synthesis tool
• Low power consumption using Low Power Synthesis tool
• Short-term development using a timing driven layout tool
• Hierarchical design environment for supporting large-scale circuits
• Support for Signal-Integrity
• Support for Memory (RAM, ROM) SCAN
• Support for Memory (RAM) BIST
• Support for Boundary SCAN
• Support for path delay test
• A variety of package options : QFP, TQFP, LQFP, HQFP, PBGA, FBGA, FLGA, EBGA


Specifications

Parameter
Symbol
Rating
Unit
Min
Max
Supply voltage
VDD
- 0.5
2.5 *1
V
4.0 *2
Input voltage
VI
- 0.5
VDD+0.5 (2.5 V) *1
V
VDD+0.5 (4.0 V) *2
Output voltage
VO
- 0.5
VDD+0.5 ( 2.5 V) *1
V
VDD+0.5 (4.0 V) *2
Storage temperature
Tst
-55
+125
°C
Junction temperature
Tj
-40
+125
°C
Output current*3
IO
±10 (3.3 VCMOS, 2.5 VCMOS)
mA
± 7.5 (1.8 VCMOS)
Input signal transmitting rate
RI
--
Clock input*4 : 200
Normal input : 100
Mbps*5
Output signal transmitting rate
RO
--
100
Mbps*5
Output load capacitance
CO
--
3000/RO
pF
Supply pin current*6
ID
For one VDD/GND pin*6
mA



Description

The CS86 series of 0.18 mm standard cells is a line of CMOS ASICs based on higher integration implemented by introducing wiring pitch reduction technology and on I/O pad placement technology to the conventional CS81 series.

The CS86 series has three types of cell sets (CS86MN, CS86MZ, and CS86ML), covering a variety of applications, from portable devices requiring low power consumption to image processors requiring large-scale circuitry and high speed.The three types of cell sets can be contained on one chip, allowing those system LSIs to be implemented which require low power consumption as well as high-speed operation for certain types of processing.




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