CS61881

The CS61881contains eight analog front ends that each provide the line interface for E1 transmission systems. The device contains eight receivers and transmitters supporting a 2.048 Mbps data rate compliant to ITU G.703. This device is commonly used with external circuitry that supplies data encoding/decoding, clock recovery, and jitter attenuation.

The CS61881 makes use of ultra low power matched impedance transmitters to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics, exceeding ETS 300 166. The internal line matching circuitry reduces the external component count and eliminates the need to change components to support both 75 Ω and 120 Ω lines. All transmitters have controls for independent power down and tristate.

The receiver CS61881 has a high noise margin, providing reliable data recovery even with cable attenuation of over 12 dB. It has an impedance matched front end, eliminating the need to change components to support both 75 Ω and 120 Ω line impedances. The receiver also incorporates LOS detection compliant to the most recent specifications.

A five wire JTAG interface is also provided for improved diagnostics and reduced manufacturing cost.