CS5331A-DS

The CS5331A-DS is one member of the CS5331A series.The CS5331A is a complete stereo analog-to-digital converter that performs anti-alias filtering, sampling and analog-to-digital conversion generating 18-bit values for both left and right inputs in serial form. The output sample rate can be infinitely adjusted between 2 kHz and 50 kHz.

Features of the CS5331A-DS are:(1)single +5 V power supply; (2)18-bit resolution; (3)94 dB dynamic range; (4)linear phase digital anti-alias filtering; (5)adjustable system sampling rates including 32kHz, 44.1 kHz & 48kHz.The ADC uses delta-sigma modulation with 128X oversampling,followed by digital filtering and decimation,which removes the need for an external anti-alias filter.The linear-phase digital filter has a passband to 21.7 kHz, 0.05 dB passband ripple and >80 dB stopband rejection. The device also contains a high-pass filter to remove DC offsets.

The absolute maximum ratings of the CS5331A-DS can be summarized as:(1)storage temperature:-65 to 150;(2)analog supply voltage:-0.3 to 6V;(3)input current, any pin except supplies:±10mA;(4)ambient temperature:-55 to 125;(5)analog input voltage:-0.7 to VA+0.7V.In master mode, SCLK and LRCK are outputs where the MCLK/LRCK frequency ratio is 256x. LRCK will appear as an output 127 MCLK cycles into the initialization sequence. At this time, power is applied to the internal voltage reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static low during the initialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kHz output sample rate).In slave mode, SCLK and LRCK are inputs where the MCLK/LRCK frequency ratio must be either 256x,384x, or 512x. Once the MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. At this time, power is applied to the internal voltage reference and the analog inputs will move to approximately 2.4 Volts. SDATA is static high during the initialization and high pass filter settling sequence, which requires 11,265 LRCK cycles (235 ms at a 48 kHz sample rate).