Features: • Technology : 0.25 mm silicon-gate CMOS, 3- to 4-layer wiring
• Supply voltage : +2.5 V ± 0.2 V (normal) to +1.5 V ± 0.1 V
• Junction temperature range : -40 °C to +125 °C
• Gate delay time : tpd = 33 ps (2.5 V, inverter cell High Speed type, F/O = 1, No load)
• Gate power consumption : 0.02 mW/MHz (1.5 V, F/O = 1, No load)
• High-load driving capability : IOL = 2 mA/4 mA/8 mA/12 mA mixable
• Output buffer cells with noise reduction circuits
• Inputs with on-chip input pull-up/pull-down resistors (25 kW typical) and bidirectional buffer cells
• Buffer cells dedicated to crystal oscillator
• Special interfaces (P-CML, LVDS, T-LVTTL, SSTL, PCI, USB, GTL+, and others including those under
development)
• IP macros (CPU, PCI, USB, IrDA, PLL, DAC, ADC, and others including those under development)
• Capable of incorporating compiled cells (RAM/ROM/FIFO/Delay line, and others.)
• Configurable internal bus circuits
• Advanced hardware/software co-design environment
• Support for static timing sign-off Dramatically reducing the time for generating test vectors for timing verification and the simulation time
• Hierarchical design environment for supporting large-scale circuits
• Simulation (before layout) considering the input slew rate and detailed RC delay calculation (after layout) , supporting development with minimized timing trouble after trial manufacture
• Support for memory (RAM/ROM) SCAN
• Support for memory (RAM) BIST
• Support for boundary SCAN
• Support for path delay test
• A variety of package options (QFP, TQFP, LQFP, HQFP, BGA, T-BGA, FCBGA under development)
Specifications
| Parameter |
Symbol |
Application |
Rating |
Unit |
|
Min |
Max |
| Supply voltage |
VDD |
VDD = 1.4 V to 2.7 V |
- 0.5
|
+3.0*3
+4.0*4 |
V |
| VDD = 2.7 V to 3.6 V |
VDD + 0.5 ( £ 3.0 V) *3 |
| Input voltage |
VI |
-- |
- 0.5 |
VDD + 0.5 ( £ 4.0 V) *4 |
V |
|
VDD + 0.5 ( £ 3.0 V) *3 |
| Output voltage |
VO |
-- |
- 0.5 |
VDD + 0.5 ( £ 4.0 V) *4 |
V |
|
+125 |
| Storage temperature |
Tst |
-- |
-55 |
+125 |
°C |
| Junction temperature |
Tj |
-- |
-40 |
±13 |
°C |
| Output current*1 |
L type |
IO |
Powerless type
(IOL = 2 mA) |
-- |
±13 |
mA |
| M type |
Nomal type
(IOL = 4 mA) |
-- |
±13 |
mA |
| H type |
Power type
(IOL = 8 mA) |
-- |
±26 |
mA |
| V type |
High power type
(IOL = 12 mA) |
-- |
60 |
mA |
| Power-supply pin current *2 |
ID |
Per VDD, GND pin |
-- |
30 |
mA |
DescriptionThe CE77 series 0.25 mm CMOS embedded array is a line of highly integrated CMOS ASICs featuring high speed and low power consumption at the same time.
CE77 series is available in 15 frames with the enhanced lineup of 470 K to 6980 K gates.
CE77 Data Sheet
