CDP1822

Features:

• Low Operating Current
- VDD = 5V, Cycle Time 1ms . . . . . . . . . . . . . . . . . . 8mA
• Industry Standard Pinout
• Two Chip-Select Inputs-Simple Memory Expansion
• Memory Retention for Standby Battery Voltage of 2V Minimum
• Output-Disable for Common I/O Systems
• Three-State Data Output for Bus-Oriented Systems
• Separate Data Inputs and Outputs


Specifications

DC Supply Voltage Range, (V_DD) (All Voltages Referenced to V_SS Terminal) CDP1822 . . . . . . . . . . . . . . . . . . . . -0.5V to +11V
CDP1822C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . . . . . .. . . . . . .-0.5V to +7V
Input Voltage Range, All Inputs . . . . . . . . . . . . .  . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .. . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .±10mA


Description

The CDP1822 and CDP1822C are 256-word by 4-bit static random-access memories designed for use in memory systems where high speed, low operating current, and simplicity in use are desirable. The CDP1822 features high speed and a wide operating voltage range. Both types have separate data inputs and outputs and utilize single power supplies of 4V to 6.5V for the CDP1822C and 4V to 10.5V for the CDP1822.
Two Chip-Select inputs are provided to simplify system expansion. An Output Disable control provides Wire-OR capability and is also useful in common Input/Output systems.
The Output Disable input CDP1822 allows these RAMs to be used in common data Input/Output systems by forcing the output into a high-impedance state during a write operation independent of the Chip-Select input condition. The output assumes a high-impedance state when the Output Disable is at high level or when the chip is deselected by CS1 and/or CS2.
The high noise immunity of the CMOS technology CDP1822 is preserved in this design. For TTL interfacing at 5V operation, excellent system noise margin is preserved by using an external pull-up resistor at each input.