CDCVF855

DescriptionThe CDCVF855 is a high-performance, low-skew,low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK ) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3] ) and one differential pair of feedback clock outputs (FBOUT, FBOUT ). The clock outputs are c...

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SeekIC No. : 004312316 Detail

CDCVF855: DescriptionThe CDCVF855 is a high-performance, low-skew,low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK ) to 4 differential pairs of clock outputs (Y[0:3], Y...

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Part Number:
CDCVF855
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/11/24

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Product Details

Description



Description

The CDCVF855 is a high-performance, low-skew,low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK ) to 4 differential pairs of clock outputs (Y[0:3], Y[0:3] ) and one differential pair of feedback clock outputs (FBOUT, FBOUT ). The clock outputs are controlled by the clock inputs (CLK, CLK ), the feedback clocks (FBIN, FBIN ), and the analog power input (AV DD ).When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency-detection circuit detects the low-frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.

Features of the CDCVF855 are:(1)Spread-Spectrum Clock Compatible; (2)Operating Frequency: 60 MHz to 220 MHz; (3)Low Jitter (Cycle-Cycle): ± 60 ps ( ± 40 ps at 200 MHz); (4)Low Static Phase Offset: ± 50 ps; (5)Low Jitter (Period): ± 60 ps ( ± 30 ps at 200 MHz); (6)1-to-4 Differential Clock Distribution (SSTL2); (7)Best in Class for V OX = V DD /2 ± 0.1 V; (8)Operates From Dual 2.6-V or 2.5-V Supplies; (9)Available in a 28-Pin TSSOP Package; (10)Consumes < 100- A Quiescent Current; (11)External Feedback Pins (FBIN, FBIN ) Are Used to Synchronize the Outputs to the Input Clocks; (12)Meets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 Specification; (13)Meets/Exceeds Proposed DDRI-400 Specification (JESD82-1A); (14)Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low.

The absolute maximum ratings of the CDCVF855 can be summarized as:(1)Supply voltage range 0.5 V to 3.6 V; (2)Input voltage range (2) (3) 0.5 V to V DDQ + 0.5 V; (3)Output voltage range (2) (3) 0.5 V to V DDQ + 0.5 V; (4)Input clamp current V I< 0 or V I> V DDQ ± 50 mA; (5)Output clamp current V O < 0 or V O > V DDQ ± 50 mA; (6)Continuous output current V O = 0 to V DDQ ± 50 mA; (7)Continuous current to GND or V DDQ ± 100 mA; (8)Storage temperature range 65 ° C to 150 ° C.

If you want to know more CDCVF855 information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .




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