CDCVF2509A

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Features of the CDCVF2509A are:(1)Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1; (2)Spread Spectrum Clock Compatible; (3)Operating Frequency 20 MHz to 175 MHz; (4)Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps; (5)Jitter (cyc - cyc) at 60 MHz to 175 MHz Is Typ = 65 ps; (6)Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices; (7)Auto Frequency Detection to Disable Device (Power-Down Mode); (8)Available in Plastic 24-Pin TSSOP; (9)Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications; (10)Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs; (11)Separate Output Enable for Each Output Bank; (12)External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input.

The absolute maximum ratings of the CDCVF2509A can be summarized as:(1)Supply voltage range (2):AVCC < VCC +0.7 V; (2)Supply voltage range :0.5 V to 4.3 V; (3)Input voltage range (3):0.5 V to 4.6 V; (4)Voltage range applied to any output in the high or low state:0.5 V to VCC + 0.5; (5)Input clamp current (VI< 0) :50 mA; (6)Output clamp current (VO< 0 or VO > VCC) :±50 mA; (7)Continuous output current (VO = 0 to VCC): ±50 mA; (8)Continuous current through each VCC or GND :±100 mA; (9)Maximum power dissipation at TA = 55°C (in still air)(5):0.7 W; (10)Storage temperature range :65°C to 150°C.

If you want to know more CDCVF2509A information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .