CDCVF2505-Q1

The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0 3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.

Features of the CDCVF2505-Q1 are:(1)Qualified for Automotive Applications; (2)Phase-Locked Loop Clock Driver for Synchronous DRAM and General-Purpose Applications; (3)Spread-Spectrum Clock Compatible; (4)Operating Frequency: 24 MHz to 200 MHz; (5)Low Jitter (Cycle-to-Cycle): < 150 ps Over the Range 66 MHz to 200 MHz; (6)Distributes One Clock Input to One Bank of Five Outputs (CLKOUT Is Used to Tune the Input-Output Delay); (7)Three-States Outputs When There Is No Input Clock; (8)Operates From Single 3.3-V Supply; (9)Available in 8-Pin SOIC Package.

The absolute maximum ratings of the CDCVF2505-Q1 can be summarized as:(1)Supply voltage range : 0.5 V to 4.3 V; (2)Input voltage range (2) (3): 0.5 V to V DD + 0.5 V; (3)Output voltage range (2) (3): 0.5 V to V DD + 0.5 V; (4)Input clamp current V I < 0 or V I > V DD :± 50 mA; (5)Output clamp current V O < 0 or V O > V DD :± 50 mA; (6)Continuous total output current V O = 0 to V DD :± 50 mA; (7)Package thermal impedance (4):97.1 ° C/W; (8)Storage temperature range: 65 ° C to 150 ° C.

If you want to know more CDCVF2505-Q1 information such as the electrical characteristics ,please download the datasheet in www.seekdatasheet.com .