CDC950DGGR

The CDC950DGGR is one member of the CDC950 series.It has the following features including (1)generates clocks for next generation microprocessors;(2)uses a 14.318-MHz crystal input to generate multiple output frequencies;(3)includes spread spectrum clocking (SSC),0.6% downspread for reduced EMI with theoretical EMI of 7 dB;(4)power management control terminals.

The CDC950 is a differential clock synthesizer/driver that generates HCLK/HCLK, CLK33, 3V48, and REFCLK system clock signals to support a computer system with next generation processors and double data rate (DDR) memory subsystems.All output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components.Since the CDC950 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.This stabilization time is required following power up, as well as following changes to the SEL inputs. With the use of an external reference clock, this signal must be fixed-frequency and fixed-phase prior to stabilization time starts. The CDC950 is characterized for operation from 0°C to 85°C.

CDC950DGGR TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other CDC950DGGR TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.