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CDC930

Features: Generates Clocks for Pentium®4 MicroprocessorsUses a 14.318 MHz Crystal Input to Generate Multiple Output FrequenciesIncludes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI Damping of 7 dB†Power Management Control TerminalsLow Output Skew ...

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SeekIC No. : 004312268 Detail

CDC930: Features: Generates Clocks for Pentium®4 MicroprocessorsUses a 14.318 MHz Crystal Input to Generate Multiple Output FrequenciesIncludes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduc...

CDC930 Data Sheet

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Part Number:
CDC930
Supply Ability:
5000

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  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

Generates Clocks for Pentium®4 Microprocessors
 Uses a 14.318 MHz Crystal Input to Generate Multiple Output Frequencies
 Includes Spread Spectrum Clocking (SSC), 0.6% Downspread for Reduced EMI With Theoretical EMI Damping of 7 dB†
 Power Management Control Terminals
 Low Output Skew and Jitter for Clock Distribution
 Operates From Single 3.3-V Supply
 Consumes Less Than 30-mA Power-Down Current
 Generates the Following Clocks:
   4 HCLK (Host) (Different Pairs 100/133 MHz)
   1 3VMREF Pair (3.3 V, 180° Shifted 50/66 MHz)
   10 PCI (3.3 V, 33.3 MHz)
   2 REF (3.3 V, 14.318 MHz)
   4 3V66 MHz (3.3 V, 66 MHz)
   2 3V48 MHz (3.3 V, 48 MHz)
 Packaged in 56-Pin SSOP Package


Pinout

Connection Diagram


Specifications

Supply voltage range, VDD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to VDD + 0.5 V
Voltage range applied to any output in the high-impedance state or power-off state,
    VO (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . .0.5 V to VDD + 0.5 V
Current into any output in the low state, IO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2* rated IOL
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . . . 18 mA
                                      (VI < VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . . 18 mA
Output clamp current , IOK (VO < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .   . . . . . . . .50 mA
                                           (VO < VDD)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .50 mA
Package thermal impedance, JA (see Note 2)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74°C/W
Maximum power dissipation at TA = 55°C (in still air) (see Note 3)  . . . . . . . . . . . . . .. . . . . . . . . . .1.3 W
Operating free-air temperature range, TA  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  . . . . . . .0°C to 85°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  . . . . . . . . . . . . .  . . . . . . . . . . . .260°C


Description

The CDC930 is a differential clock synthesizer/ driver that generates HCLK/HCLK, 3VMREF/ 3VMREF, PCI, 3V66, 3V48, REF system clock signals to support a computer system with a Pentium®4 microprocessor and a Direct RambusTM memory subsystem.

All CDC930 output frequencies are generated from a 14.318-MHz crystal input. A reference clock input can be provided at the XIN input instead of a crystal. Two phase-locked loops (PLLs) are used to generate the host frequencies and the 48-MHz clock frequencies. On-chip loop filters and internal feedback eliminate the need for external components. The host, PCI clock and 48-MHz clock outputs provide low-skew/low-jitter clock signals for reliable clock operation. All CDC930 outputs have 3-state capability, which can be selected using control inputs SEL133, SelA and SelB.
 
The CDC930 outputs are either differential host clock or 3.3-V single-ended CMOS buffers. When PWRDWN is set to high, the device operates in normal mode. When PWRDWN is set low, the device transitions to a power-down mode in which HCLK is driven at 2×IREF, HCLK is not driven, and all others are set low.




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