CDC925

Specifications

Supply voltage range, VDD  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4.6 V
Voltage range applied to any output in the high-impedance state or power-off state, VO (see Note 1)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VDD + 0.5 V
Current into any output in the low state, IO  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 * IOL
Input clamp current, IIK (VI < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 mA
Output clamp current, IOK (VO < 0)  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Operating free-air temperature range, TA  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 85°C
Storage temperature range, Tstg  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C

† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.


Description

The CDC925 is a clock synthesizer/driver that generates system clocks necessary to support Intel Pentium III systems on CPU, CPU_DIV2, 3V66, PCI, APIC, 48MHz, and REF clock signals. All CDC925 output frequencies are generated from a 14.318-MHz crystal input. A reference clock input instead of a crystal can be provided at the XIN input. Two phase-locked loops (PLLs) are used, one to generate the host frequencies and the other to generate the 48-MHz clock frequency. On-chip loop filters and internal feedback loops eliminate the need for external components.
The host and PCI clock outputs CDC925 provide low-skew and low-jitter clock signals for reliable clock operation. All CDC925 outputs have 3-state capability, which can be selected via control inputs SEL0, SEL1, and SEL133/100.
The CDC925 outputs are either 3.3-V or 2.5-V single-ended CMOS buffers. With a logic high-level on the PWR_DWN terminal, the device operates normally, but when a logical low-level input is applied, the device powers down completely, with the outputs in a low-level output state. When a high-level is applied to the PCI_STOP or CPU_STOP, the outputs operate normally. With a low-level applied to the PCI_STOP or CPU_STOP terminals, the PCI or CPU and 3V66 outputs, respectively, are held in a low-level state.
The CPU bus CDC925 can operate at 100 MHz or 133 MHz. Output frequency selection is done with corresponding setting for SEL133/100 control input. The PCI bus frequency is fixed to 33MHz.