CD74HCU04

Features: Typical Propagation Delay: 6ns at VCC = 5V,CL = 15pF, TA = 25oC, Fastest Part in QMOS LineWide Operating Temperature Range . . . -55oC to 125oCBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsHCU Types- 2V to 6V Operation- High Noise I...

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SeekIC No. : 004312193 Detail

CD74HCU04: Features: Typical Propagation Delay: 6ns at VCC = 5V,CL = 15pF, TA = 25oC, Fastest Part in QMOS LineWide Operating Temperature Range . . . -55oC to 125oCBalanced Propagation Delay and Transition Tim...

floor Price/Ceiling Price

Part Number:
CD74HCU04
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/31

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Product Details

Description



Features:

Typical Propagation Delay: 6ns at VCC = 5V,CL = 15pF, TA = 25oC, Fastest Part in QMOS Line
Wide Operating Temperature Range . . . -55oC to 125oC
Balanced Propagation Delay and Transition Times
Significant Power Reduction Compared to LSTTL Logic ICs
HCU Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 20%, NIH = 30% of VCC at VCC = 5V
CMOS Input Compatibility, Il £ 1mA at VOL, VOH



Pinout

  Connection Diagram


Specifications

DC Supply Voltage, VCC
Voltages Referenced to Ground . . . . . . . . . . . . . . . . . . . . . . .-0.5V to +7V
DC Input Diode Current, IIK
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, IO
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . ..  . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . ..±50mA



Description

The Harris CD74HCU04 unbuffered hex inverter utilizes silicongate CMOS technology to achieve operation speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits. CD74HCU04 are especially useful in crystal oscillator and analog applications. Figures 10 and 11 are supplied as design information for the above applications.


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