CD74HCT7046A

The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified incompliance with JEDEC Standard No.7A, are phase-locked-loop (PLL) circuits that contain aline arvoltage-controlledo scillator (VCO) ,two-phase comparators (PC1,PC2),and alock detector .A signal input an dacomparator in put are common to each comparator.The lock detector gives a HIGH level at pin1(LD) when the PLLis locked.The lock detector capacitor must be connected between pin15(CLD)and pin 8(Gnd). For afrequency range of 100k Hzto10 MHz,the lock detector capacitor should be 1000pF to10pF, respectively.

CD74HCT7046A signal in put can be directly coupled to large voltage signals, orindirectly coupled (with aseries capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals with in the lin earregi on of the input amplifiers. With apassive low-pass filter,the 7046A for msasecond-oderlooPLL.The excellent VCO linear CD74HCT7046A yi sa chieved by the use of linear op-amp techniques.