Features: • Buffered Inputs• Asynchronous Parallel Load• Fanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads• Wide Operating Temperature Range . . . -55to 125• Balance...
CD74HCT597: Features: • Buffered Inputs• Asynchronous Parallel Load• Fanout (Over Temperature Range)Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads Bus Driver Outputs . . . . . ....
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DC Supply Voltage, VCC .................................................................. -0.5V to 7V
DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V ..............±20mA
DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V .........±20mA
DC Output Source or Sink Current per Output Pin, IO
For VO > -0.5V or VO < VCC + 0.5V ............................................................25mA
DC VCC or Ground Current, ICC or IGND ..................................................±50mA
The 'HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin-compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR) clears the shift register. CD74HCT597 Serial input data can also be synchronously shifted through the shift register when PL is high.