CD74HC595

Features:

·8-Bit Serial-In, Parallel-Out Shift
·Wide Operating Voltage Range of 2 V to 6 V
·High-Current 3-State Outputs Can Drive Up To 15 LSTTL Loads
·Low Power Consumption, 80-µA Max ICC
·Typical tpd = 14 ns
·±6-mA Output Drive at 5 V
·Low Input Current of 1 µA Max
·Shift Register Has Direct Clear

Pinout




Specifications

Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .−0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1)  . . . . . . . . . . . . . . . . . . . . .±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1)  . . . . . . . .   . . . . . . . . .±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35 mA
Continuous current through VCC or GND  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .±70 mA
Package thermal impedance, JA (see Note 2): E package  . . . . . . . . . . .  . . . . . . . . .67°C/W
                                                                          DW package  . . . . . . . . . . . . . . . . . . .57°C/W
                                                                          M package . . . . . . . . . . . . . . . . . . . . .73°C/W 
                                                                          NS package . . . . . . . . . . . .  . . . . . . . .64°C/W 
                                                                          SM package  . . . . . . . . . . . . . . . . . . . .82°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C


Description

The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. The storage register has parallel 3-state outputs. Separate clocks are provided for both the shift and storage registers. The shift register has a direct overriding clear (SRCLR) input, serial (SER) input, and serial output for cascading. When CD74HC595 output-enable (OE) input is high, the outputs are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together,CD74HC595 shift register always is one clock pulse ahead of the storage register.