Features: • Positive or Negative Edge Triggering• Synchronous Internal Carry Propagation• Fanout (Over Temperature Range) Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads• Wide Operating Temperature Range...
CD74HC4520: Features: • Positive or Negative Edge Triggering• Synchronous Internal Carry Propagation• Fanout (Over Temperature Range) Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Load...
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• Positive or Negative Edge Triggering
• Synchronous Internal Carry Propagation
• Fanout (Over Temperature Range)
Standard Outputs. . . . . . . . . . . . . . .10 LSTTL Loads
Bus Driver Outputs . . . . . . . . . . . . .15 LSTTL Loads
• Wide Operating Temperature Range . . .-55Cto 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
2V to 6V Operation
High Noise Immunity: NIL= 30%, NIH = 30% of VCC
at VCC = 5V
• HCT Types
4.5V to 5.5V Operation
Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH= 2V (Min)
CMOS Input Compatibility, Il1µA at VOL, VOH
The CD74HC4518 is adual BCD up-counter.The'HC4520 and CD74HCT4520 are dual binary up-counters.Each CD74HC4520consists of two independent internally synchronous 4-stagecounters.The counter stages are D-type flip-flops having inter change able CLOCK and ENABLE lines for in crementing one ither the positive-going or the negative going ransition of CLOCK.The counters are cleared by high level son the MASTERRESET lines.
CD74HC4520 counter can be cascaded in the rip plemode by connectingQ3 to the ENABLE in putofthes ubse quent counter while the CLOCK input of the latter is held low.