CD74HC147

Features:

•Buffered Inputs and Outputs
• Typical Propagation Delay: 13ns at V_CC = 5V, C_L = 15pF, T_A = 25
• Fanout (Over Temperature Range)
   - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
   - Bus Driver Outputs . . . . . . . . . . . .... . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55 to 125
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
   - 2V to 6V Operation
   - High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC at V_CC = 5V
• HCT Types
   - 4.5V to 5.5V Operation
   - Direct LSTTL Input Logic Compatibility, V_IL= 0.8V (Max), V_IH = 2V (Min)
   - CMOS Input Compatibility, I_l 1A at V_OL, V_OH


Pinout




Specifications

DC Supply Voltage, V_CC . . . . . . . . . . . . . . . . . . . . ...... . . . -0.5V to 7V
DC Input Diode Current, I_IK
For V_I < -0.5V or V_I > V_CC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, IOK
For V_O < -0.5V or V_O > V_CC + 0.5V . . . . . . . . . . . . . . . . ... . . .±20mA
DC Output Source or Sink Current per Output Pin, I _O
For V_O > -0.5V or V_O < V_CC + 0.5V . . . . . . . . . . . . . . . . . ... . .±25mA
DC V_CC or Ground Current, I_CC or I_GND . . . . . . . . . . . . . . .. . .±50mA


Description

The 'HC147 and CD74HCT147 are high speed silicon-gate CMOS devices and are pin-compatible with low power Schottky TTL (LSTTL).

The 'HC147 and CD74HCT147 9-input priority encoders accept data from nine active LOW inputs (l₁ to l₉) and provide binary representation on the four active LOW inputs (Y0 to Y3). A priority is assigned to each input so that when two or more inputs are simultaneously active, the input with
the highest priority is represented on the output, with input line l9 having the highest priority.

CD74HC147 provide the 10-line to 4-line priority encoding function by use of the implied decimal "zero". The "zero" is encoded when all nine data inputs are HIGH, forcing all four outputs HIGH.