CD74HC08-Q1

Supply voltage range, V_CC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input clamp current, I_IK (V_I < 0.5 V or V_I > V_CC + 0.5 V) (see Note 1) . . . . ±20 mA
Output clamp current, I_OK (V_O < 0.5 V or V_O > V_CC + 0.5 V) (see Note 1) . .±20 mA
Continuous output current, I_O (V_O > 0.5 or V_O < V_CC + 0.5 V) . . . . . . . . . . .±25 mA
Continuous current through V_CC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, _JA (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . .180°C/W
Maximum junction temperature, T_J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  150°C
Lead temperature (during soldering):
At distance 1/16 ± 1/32 inch (1,59 ± 0,79 mm) from case for 10 s max . . . . . .  300°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
† Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.

The CD74HC08 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates, with the low power consumption of standard CMOS integrated circuits. CD74HC08-Q1 can drive 10 LSTTL loads.