Features: BiCMOS Technology With Low Quiescent PowerBuffered InputsInverted OutputsInput/Output Isolation From VCCControlled Output Edge Rates48-mA Output Sink CurrentOutput Voltage Swing Limited to 3.7 V SCR Latch-Up-Resistant BiCMOS Process and Circuit DesignPackaged in Plastic Small-Outline Pac...
CD74FCT842A: Features: BiCMOS Technology With Low Quiescent PowerBuffered InputsInverted OutputsInput/Output Isolation From VCCControlled Output Edge Rates48-mA Output Sink CurrentOutput Voltage Swing Limited to...
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The CD74FCT842A is a 10-bit, D-type latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device provides extra data width for wider address/data paths or buses carrying parity. The latches are transparent D-type latches. The device provides inverted outputs.
CD74FCT842A uses a small-geometry BiCMOS technology. The CD74FCT842A output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and ground bounce and their effects during simultaneous output switching. The output configuration also enhances switching speed and is capable of sinking 48 mA.
The CD74FCT842A outputs are transparent to the inputs when the latch-enable (LE) input is high. When LE goes low, the data is latched. The output-enable (OE) input controls the 3-state outputs. When OE is high, the outputs are in the high-impedance state. The latch operation is independent of the state of OE.
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can be entered while the outputs are in the high-impedance state.
The CD74FCT842A is characterized for operation from 0°C to 70°C.